Defect-Sensitivity Analysis of an SEU Immune CMOS Logic Family *
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چکیده
Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate and an evaluation of its ability to cope with them is determined.
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تاریخ انتشار 2008